Ensure the absence of security weaknesses.
Radix-S is used during design creation and verification to detect and remediate security issues in IP blocks and subsystems of an SoC. Its advanced information flow analysis helps teams identify and locate the root cause of potentially serious security issues and provides a more comprehensive validation technique for internal security requirements.
Radix-S automates and enhances the security review processes by more efficiently creating pass/fail security rules directly from security requirements, which can be easily validated by using common simulators from Cadence, Synopsys, and Siemens EDA. These rules are orders of magnitude more compact than traditional functional assertions and provide significantly broader security coverage. Moreover, their simplicity and expressiveness enable greater collaboration between security experts and hardware designers.
In addition, Radix-S helps identify 80% of common hardware weaknesses in the Common Weakness Enumeration (CWE) database maintained by MITRE.
Identify security rule violations
Leverage existing tests for information flow tracking
Integrate into existing verification simulation
The inputs to Radix-S include the System IP or SoC’s RTL files, a set of security rules, along with the block or system level test bench files that verification teams are already developing. Radix-S then creates and adds a hardware Security Model to the design. The Security Model is used to check the validity of the security rules while running in a commercially available simulator.
Radix-S addresses a wide range of critical security verification challenges, including:
Detect and prevent Meltdown / Spectre variants of attacks.
Ensure keys remain secure during and after usages.
Verifies that vulnerabilities have not been introduced due to integration errors.