RADIX-ST
Static Security Analysis
Identify and resolve security weaknesses earlier in chip design.
Uncover Hardware Security Risks With Greater Efficiency
Radix-ST is a static security analyzer designed to identify potential design weaknesses early in the development lifecycle without requiring simulation or emulation.
Unlike basic source code linting tools, Radix-ST performs deep security analysis of your RTL designs, seamlessly integrating with the Radix security assurance workflow to deliver actionable vulnerability insights that pinpoint the location of security issues in the source code and map them to relevant hardware Common Weakness Enumeration (CWEs).
Radix-ST Benefits:
Early Security Analysis
Identify and rectify security vulnerabilities at the earliest stages of development, with minimal user input.
Focused Security Insights
Utilize the Common Weakness Enumeration (CWE) knowledgebase to acquire in-depth knowledge of potential security vulnerabilities and ensure that designs adhere to industry best practices.
Seamless Integration with Radix Workflow
Leverage the Radix-ST aligned workflow and GUI with Radix-S and Radix-M to comprehensively execute security verification from the initial RTL code to system integration.
RADIX-ST VIDEO OVERVIEW
Introducing Radix-ST for Static Security Analysis
Radix-ST Features:
Automated RTL Inspection
No test bench or constraints required.
Proprietary Detection Engines
High accuracy, minimal false positives.
Integrated Reporting
Highlighted violations within the RADIX GUI.
Cross-view Navigation
Interact across Radix source, schematic, and cone views.
Radix-ST Workflow
